Single-/Dual-Band 802.11a/b/g
World-Band Transceiver ICs
PA Bias DAC Register Definition (A3:A0 = 1010)
This register controls the output current of the DAC,
which biases the external PA (see Table 18).
Rx Gain Register Definition (A3:A0 = 1011)
This register sets the Rx baseband and RF gain when
A3:A0 = 1000, D12 = 1 (see Table 19).
Tx VGA Gain Register Definition (A3:A0 = 1100)
This register sets the Tx VGA gain when A3:A0 = 1001,
D10 = 1 (see Table 20).
Applications Information
MIMO Applications
The MAX2828/MAX2829 support multiple input multiple
output (MIMO) applications where multiple transceivers
are used in parallel. A special requirement for this appli-
cation is that all receivers must maintain a constant rela-
tive local oscillator phase, and that they continue to do so
after any receive-transmit-receive mode switching. The
same requirement holds for the transmitters—they should
all maintain a constant relative phase, and continue to do
so after any transmit-receive-transmit mode switching.
This feature is enabled in the MAX2828/MAX2829 by pro-
gramming A3:A0 = 0010, D13 = 1 and A3:A0 = 0101,
D13 = 1. The constant relative phases of the multiple
transceivers are maintained in the transmit, receive, and
standby modes of operation, as long as they are all using
a common external reference frequency source (crystal
oscillator).
DESCRIPTION
D13 0
D12 0
D11 0
D10 0
Set to 0
D9 1
D8 1
D7 1
D6 1
Sets PA bias DAC turn-on delay
after TXENA is set high and A3:A0
= 0010, D10 = 1, in steps of 0.5µs.
D9:D6 = 0001 corresponds to 0µs
and 1111 corresponds to 7µs.
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Sets PA bias DAC output current in
steps of 5µA. D5:D0 = 000000
corresponds to 0µA and 111111
corresponds to 315µA.
DESCRIPTION
D13 0
D12 0
D11 0
D10 0
D9 0
D8 0
D7 0
D6 0
Not Used. For faster Tx VGA gain
setting, only D5:D0 need to be
programmed.
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Tx VGA Gain Control. D5 maps to
digital input pin B6 and D0 maps to
digital input pin B1. D5:D0 =
000000 corresponds to minimum
gain.
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