Single-/Dual-Band 802.11a/b/g
World-Band Transceiver ICs
Band-Select and PLL Register Definition
(A3:A0 = 0101)
This register configures the programmable-reference
frequency dividers for the synthesizers, and sets the
DC current for the charge pump. The programmable-
reference frequency divider provides the reference fre-
quencies to the phase detector by dividing the crystal
oscillator frequency (see Table 13).
Calibration Register Definition (A3:A0 = 0110)
This register configures the Rx/Tx calibration modes
(See Table 14).
DATA BIT DEFAULT DESCRIPTION
D13 0 Set to 0 for Normal Operation. Set to 1 for MIMO applications.
D12 1
D11 1
Set D12:D11 = 11
D10 0
D9 0
These Bits Set the VCO Sub-Band when Programmed Using the SPI (D8 = 1). D10:D9 = 00: lowest
frequency band; 11: highest frequency band.
D8 0
VCO SPI Bandswitch Enable. 0: disable SPI control, bandswitch is done by FSM; 1: bandswitch is
done by SPI programming.
D7 0 VCO Bandswitch Enable. 0: disable; 1: start automatic bandswitch.
D6 0
RF Frequency Band Select in 802.11a Mode (D0 = 1). 0: 4.9GHz to 5.35GHz Band; 1: 5.47GHz to
5.875GHz Band.
D5 1 PLL Charge-Pump-Current Select. 0: 2mA; 1: 4mA.
D4 0 Set to 0
D3 0
D2 1
D1 0
These Bits Set the Reference-Divider Ratio. D3:D1 = 001 corresponds to R = 1 and 111
corresponds to R = 7.
D0 0 RF Frequency Band Select. 0: 2.4GHz Band; 1: 5GHz band.
Table 13. Band-Select and PLL Register (A3:A0 = 0101)
DEFAULT
DESCRIPTION
D13 0 Set to 0
D12 1
D11 1
Transmitter I/Q Calibration LO
Leakage and Sideband-Detector
Gain-Control Bits. D12:D11 = 00:
8dB; 01: 18dB; 10: 24dB; 11: 34dB
D10 1 Set to 1
D9 0
D8 0
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
Set to 0
D1 0
0: Tx Calibration Mode Disabled; 1:
Tx Calibration Mode Enabled (Rx
outputs provide the LO leakage and
sideband-detector signal)
D0 0
0: RX Calibration Mode Disabled; 1:
Rx Calibration Mode Enabled
Table 14. Calibration Register
(A3:A0 = 0110)
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