Single-/Dual-Band 802.11a/b/g
World-Band Transceiver ICs
The following steps should be followed:
1) Set D8 = 0 (A3:A0 = 0101) to enable the automatic
VCO sub-band selection by the FSM.
2) Enable the PLL and VCO if required. If required,
program the divider ratios corresponding to the
desired channel frequency.
3) Set D7 = 1 (A3:A0 = 0101) to start the FSM. The FSM
should only be started after PLL and VCO are
enabled, or after channel frequency is changed.
4) The VCO sub-band selection and PLL settling time
takes less than approximately 300µs. After the
band switching is completed and the PLL has
locked to the correct channel frequency, the FSM
stops automatically.
Every time the channel frequency is programmed or the
PLL+VCO is enabled, the FSM needs to be reset to be
used again for the next time. This reset operation does
not affect the PLL or VCO. To reset the FSM, set D7 = 0
(A3:A0 = 0101).
Every channel frequency maps to some VCO sub-
band. Each VCO sub-band has a digital code, of which
the 2 LSBs (B1:B0) are readable. The B1:B0 code can
be read through pin LD by programming D3:D0 = 0111
(A3:A1 = 0000) for B1, or D3:D0 = 0110 (A3:A1 = 0000)
for B0 (see Table 6).
Manual VCO Sub-Band Selection
For faster settling, the VCO sub-band (B1:B0) can be
directly programmed through the SPI. First, the B1:B0
code for every channel frequency must be determined.
Once this is known, the B1:B0 code is directly pro-
grammed along with the PLL divider values, for the
given channel frequency. The PLL settling time in this
case is approximately 50µs.
Large temperature changes (>+50°C) may cause the
channel frequency to move into an adjacent sub-band.
To determine the correct sub-band, two on-chip com-
parators monitor the VCO control voltage (V
TUNE
).
These comparator logic outputs can be read through
the LD pin to decide whether the frequency sub-band
is correct or needs to be reprogrammed.
The following steps need to be followed to complete
manual PLL frequency acquisition and VCO sub-band
selection:
1) Set D8 = 1 (A3:A0 = 0101) to enable manual VCO
sub-band selection.
2) Enable the PLL and VCO if required. If required,
program the divider ratios corresponding to the
desired channel frequency.
3) Set D10:D9 (A3:A0 = 0101) to program the VCO
frequency sub-band according to Table 7. D10:D9
correspond to the same assignments as B1:B0.
After D10:D9 are programmed, 50µs is required to
allow the PLL to settle.
4) After 50µs of PLL settling time, the comparator out-
puts can be read through pin LD (see Table 8).
5) Based on the comparator outputs, the VCO frequen-
cy sub-band is programmed again according to
Table 8 until the frequency acquisition is achieved.
Large Temperature Changes
If the PLL and VCO are continuously active (i.e., no
reprogramming) and the die temperature changes by
50°C (as indicated by the on-chip temperature sensor),
there is a possibility that the PLL may get unlocked due
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