Single-/Dual-Band 802.11a/b/g
World-Band Transceiver ICs
grammed. The interface can be programmed through
the 3-wire SPI/MICROWIRE™-compatible serial port.
On startup, it is recommended to reset all registers by
placing the device in SPI reset mode (Table 5).
Standby Register Definition (A3:A0 = 0010)
Various internal blocks can be turned on or off using
the standby register (in standby mode, see Table 10).
Setting a bit to 1 turns the block on, while setting a bit
to 0 turns the block off.
Integer-Divider Ratio Register Definition
(A3:A0 = 0011)
This register contains the integer portion of the divider
ratio of the synthesizer. This register, in conjunction with
the fractional-divider ratio register, permits selection of a
precise frequency. The main synthesizer divide ratio is
an 8-bit value for the integer portion (see Table 11). Valid
values for this register are from 128 to 255 (D7–D0). The
default value is 210. D13 and D12 are reserved for the 2
LSBs of the fractional-divider ratio.
Fractional-Divider Ratio Register Definition
(A3:A0 = 0100)
This register (along with D13 and D12 of the integer-
divider ratio register) controls the fractional-divider ratio
with 16-bit resolution. D13 to D0 of this register com-
bined with D13 and D12 of the integer-divider ratio reg-
ister form the whole fractional-divider ratio (see Tables
12a and 12b).
A3:A0 = 0100, D13:D0 (hex) A3:A0 = 0011, D13:D12 (hex)
2412 160.8000 1010 0000 3333 00
2417 161.1333 1010 0001 0888 10
2422 161.4667 1010 0001 1DDD 11
2427 161.8000 1010 0001 3333 00
2432 162.1333 1010 0010 0888 10
2437
162.4667 1010 0010 1DDD 11
2442 162.8000 1010 0010 3333 00
2447 163.1333 1010 0011 0888 10
2452 163.4667 1010 0011 1DDD 11
2457 163.8000 1010 0011 3333 00
2462 164.1333 1010 0100 0888 10
2467 164.4667 1010 0100 1DDD 11
2472 164.8000 1010 0100 3333 00
2484 165.6000 1010 0101 2666 01
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