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Maxim DS33Z41 Manual de usuario Pagina 20

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(INPUT)
PROC (FPGA) AUTOMATICALY IMPLEMENTS BUS MODE
HW MODE PINS ARE OUTPUTS FROM Z MODULE TO PROC
LED+TP
(OUTPUT)
DS33Z11/Z41
3C2^
3D2^
5B1<
3C2^
3D2^
5B2<
3C2^
3C2^
3C2^
3C2^
3D2^
3C1^
9D4<
3C1^
9D2<
3D1^
9D4<
3D2^
3D2^
3D2^
5A6<>3D1^
TP35
U18
RB174
J29
TP72
TP71
TP78
TP74
TP75
TP77
UXB06
RB359
RB342
DS44
UXB08
TP53
DS39
R197
TP36
SW26
SW25
SW24
R74
RB173
RB176
RB175
R55
RB178
RB177
Y13
RB345
RB343
RED
330
ZADDR0
JTDI
JTDO
RCLKI
ZMOSI
ZADDR1
ZADDR0
ADDR<9..0>
7
5
TDEN
INT
30
9
4
6
3
6
0
1
RED
330
5
10K
0
1
10K
2
30
2
3
4
7
ZADDR2
JTCLK
JTMS
JTDO
ADDR<9..0>
JTDI
TCK_NU
TXD2<1>
TXD3<1>
MDC
MDIO
30
30
TX_EN<1>
RDEN
TSER
RSER
TCLKI
30
30
TXD1<1>
TXD0<1>
JMP_3
JTRST
TDO_NU
8
ZSPICS
ZSPISCK
ZMISO
2.7V
TDI_NU
TMS_NU
DAT<7..0>
VALUE=30
VALUE=30
JTMS
JTRST
JTCLK
ZADDR2
ZMISO
ZSPISCK
ZADDR1
ZMOSI
COL_DET<1>
RXD1<1>
RXD3<1>
RXDV<1>
CKPHA
SCANMOD
SCANEN
AFCS
H10S
FULLDS
RMIIMIIS
DCEDTES
MODEC1
MODEC0
HWMODE
RESET_B
WR
ZSPICS
CS
RD
INT
RXD2<1>
TX_CLK<1>
RXD0<1>
RX_CLK<1>
RX_CRS<1>
RX_ERR<1>
REF_CLKO
30
BUFFER
BUFFER
REF_CLK
09/16/2004
1/6(BLOCK)
5/71(TOTAL)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
CR-5 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE1
1
2
4
11
2
4
1
1 1 1111
65
4
9
7
3
10
8
1
2
B11
E10
E9
A10
B12
C8
E13
C7
F7
E6
D4
A2
A3
B3
A4
C3
B4
A6
A7
B6
F1
C2
B7
B1
A1
B2
C12
C5
C6
A5
B5
F5
H2
E4
D9
C9
B13
C11
A11
D10
G2
F6
E8
E7
C10
B10
A9
C4
A13
D7
D6
D5
D8
E2
B8
C1
E5
C13
E1
F3
D11
F2
D13
A8
B9
H1
1
6
2
8
7
3
4
5
4
4
4
5B2<>
5A3<>
5A3<>
5B4<>
5C3<
5C3<
5A6>
3D1^
5C3<
5D5<
5D5<
5D5<>
5D5<
8C5<
8C5<
8B4>
8B4>
8C5<
8C5<
8D5<
5D5<
5A5>
5B4<>
5B4<>
5A3<>
5A3<>
5A3<>
5A2<>
5C2>
5C2<
5B2<>
5C2<
8C3>
8C3>
8C3>
8C3>
9B4<
9B2<
9B4<
9C2<
9C4<
9C2<
9C4<
9D2<
3D2^
8B4<
5C2<
8C3>
8C5<
8D3>
8C3>
8C3>
8C3>
8A1<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
D
D
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
V3_3
SP3T
SP3T
SP3T
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
OUT
IO
IN
IN
IN
OUT
IN
IN
IN
IN
IO
V3_3
JTAG
LINE IO
MICRO PORT/SPI MASTER PORT
MII/RMII PORTS
DS33Z11_U3
RSER
TXD<0>
TX_CLK
REF_CLK
TSER
RXD<2>
INT*
RD*/DS*
MDIO
JTDO
CS*
SPI_CS*
WR*/RW*
RST*
HWMODE
MODEC<0>
MODEC<1>
DCEDTES
RMIIMIIS
FULLDS
H10S
AFCS
SCAN/EN
SCAN/MODE
CKPHA
RCLKI
RXDV
RXD<3>
RXD<1>
COL_DET
TXD<1>
TXD<2>
JTDI
RDEN/RBSYNC
TDEN/TBSYNC
D<3>
D<0>/MOSI
D<7>
D<6>
MDC
A<3>
A<0>
A<1>
D<5>
A<4>
TCLKI
D<4>
D<2>/SPICK
D<1>/MISO
A<9>
A<7>
A<8>
A<6>
A<5>
A<2>
JTCLK
JTRST
JTMS
QOVF
REF_CLKO
RX_CRS/CRS_DV
RX_ERR
RX_CLK
TXD<3>
TX_EN
RXD<0>
OUT
OUT
OUT
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
NC7SZ86_U
V3_3
NC7SZ86_U
IN
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