Maxim DS33Z41 Manual de usuario descargar pdf (Pagina 15)

DS33Z41DK

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CONTROL REGISTERS

Bit # 7 6 5 4 3 2 1 0

Name — — B5 B4 B3 B2 B1 B0

Default — — — — 0 0 0 0

Bits 5 to 0: B5 to B0. Number of frame delay for a given line.

Bit # 7 6 5 4 3 2 1 0

Name LB MC IR tgapclk rgapclk comm_tclk common_rclk z41_mode

Default 0 — — 1 1 0 0 0

Bit 7: LB

0 = Normal operation, traffic goes from the Z chip through the FPGA and to the DS21458.

1 = Loopback, Z chip rser is driven by Z chip tser. Clocks, and frame sync for Z41, are still driven by DS21458.

Bit 6: INVERT_RCLKh

0 = Do not invert RCLK.

1 = Invert RCLK.

Bit 5: MclkHiBpclkLow

0 = Use BPCLK for clock signals below.

1 = Use MCLK for clock signals below.

This signal drives the following clocks: TCLK (when bit for common_tclk is set); RCLK (when bit for common_rclk is

set); TSYSCLK and RSYSCLK (when bit for Z41_mode is set).

Bit 4: TGAPCLK

0 = Drive internal TGAPCLKx signal with TCLKx.

1 = Drive internal TGAPCLKx signal with TGAPCLK pin.

Bit 3: RGAPCLK

0 = Drive internal RGAPCLKx signal with RCLKx.

1 = Drive internal RGAPCLKx signal with RGAPCLK pin.

Bit 2: Common TCLK

0 = Drive TCLKx with internal TGAPCLKx signal (see bit 4)

1 = Drive Z chip TCLKx with BPCLK

Bit 1: Common RCLK

0 = Drive RCLKx with internal RGAPCLKx signal (see bit 3).

1 = Drive Z chip RCLKx with BPCLK.

Bit 0: Z41 Mode

0 = Not in Z41 mode.

1 = In Z41 mode.

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Maxim DS33Z41 Manual de usuario Pagina 15