
FLASH ENABLE
INTERNAL
XTAL W/ PLL
MASTER MODE
FULL DRIVE
RESET CONFIGURATION
BOOT
INTERN/EXTERN
BOOT EXT
BOOT INTERNAL
WHEN SET FOR
D18 HAS A 10.5K LOAD TO V3V
RESET AND CHIP CONFIGURATION
D18 HAS A 10K LOAD TO GND
2
1
2
1
2
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
INT5
INT4
INT3
30
PA<17..1>PA<17..1>
PD<23..16>
PD<31..24>
PD<18>
PD<19>
PD<28>
PD<22>
USERFPGA2
PD<23>
PD<21>
BIS0OBSXI
RCON
BIS1OBSXI
PD<16>
BTS_OBSXI
PD<17>
FLASH_VPP
PD<26>
16
10K
10K
10K
10K
10K
10K
10K
17
10K
1.0K
10K
1.0K
1.0K
1.0K
1.0K
18
I69
ECJ-2VB1C104K
.1UF
0L_SMT0805_10PCT
AMBER
I65
1.0K
1.0K
1.0K
20
9
10
11
12
8
7
6
5
19
13
14
16
15
17
4
3
2
1
24
21
25
26
27
28
29
30
31
10K
22
9
10
11
12
13
14
16
17
23
8
7
6
5
4
3
2
1
15
I18
OE
EB1
CS0
NA
CY62128V
CY62128V
I54
OE
EB0
CS0
NA
CY62128V
CY62128V
14/71(TOTAL)
2/7(BLOCK)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
19
18
14
21
15
20
17
13
31
27
28
10
26
11
25
12
9
32
16
24
29
1
23
2
3
4
5
6
7
8
30
22
U26
R229
19
21
18
15
17
14
20
13
28
27
31
4
26
3
25
2
5
32
16
24
29
1
23
12
11
10
9
8
7
6
30
22
U30
R79
R07
R248
1
2
DS20
R83
C12
2
7
8
16
15
12
11
10
9
6
5
4
3
14
13
1
SW06
R12
R16
2
1
R254
2
1
R255
R230
2
1
R160
R152
R236
2
1
R235
R233
R232
2
1
R231
R234
2
1
R196
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
D
D
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V5_0
SWITCH
8 POS
V3_3
V3_3
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
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