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DS33Z41 Quad IMUX Ethernet Mapper
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Figure 8-3. IMUX Interface to T1/E1 Transceivers
T1E1
T1E1
T1E1
T1E1
LIU
LIU
LIU
LIU
Framer
Framer
Framer
Framer
I
B
O
TSER
RSER
TSYNC
RSYNC
Line 1
IMUX
Ethernet Port
Arbiter
SDRAM
Interface
H
D
L
C
T1E1
T1E1
TCLKI
RCLKI
Figure 8-4. Diagram of Data Transmission with IMUX Operation
. . .
. . .
. . .
. . .
Sequence 01
L1 03
L2 03
L3 03
L4 03
L1 04
L2 04
L3 04
L4 04
L1 31
L2 31
L3 31
L4 31
L1 32
L2 32
L3 32
L4 32
s01
s01
s01
s01
xxxx
xxxx
xxxx
xxxx
. . .
. . .
. . .
. . .
Sequence 02
L1 03
L2 03
L3 03
L4 03
L1 04
L2 04
L3 04
L4 04
L1 31
L2 31
L3 31
L4 31
L1 32
L2 32
L3 32
L4 32
s02
s02
s02
s02
xxxx
xxxx
xxxx
xxxx
LINK 1
LINK 2
LINK 3
LINK 4
FRAMER IBO
128 Byte Sequence 01 128 Byte Sequence 02
. . .
. . .
L1 03L2 03L3 03L4 03L1 04L2 04L3 04L4 04L1 31L2 31 L3 31 L4 31 L1 32 L2 32 L3 32 L4 32 s01 s01 s01 s01 xxxxxxxxxxxxxxxx
B
y
te Se
q
uence Detail
. . .
N N+1N+2N+3N+4N+5N+6N+7N+119 N+120
. . .
From TSER
Encapsulated
Packet Byte:
Data on IBO Bus
TSYNC:
Time
Sequence
Numbers
Signaling
Channel
- DS33Z41 1
- Quad IMUX Ethernet Mapper 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1 DESCRIPTION 7
- 2 FEATURE HIGHLIGHTS 8
- 2.6 SDRAM Interface 9
- 2.7 MAC Interface 9
- 2.9 Test and Diagnostics 9
- 3 APPLICATIONS 11
- 4 ACRONYMS AND GLOSSARY 12
- 5 MAJOR OPERATING MODES 13
- 6 BLOCK DIAGRAMS 13
- 7 PIN DESCRIPTIONS 14
- 8 FUNCTIONAL DESCRIPTION 22
- 8.1 Processor Interface 23
- 8.2 Clock Structure 24
- Table 8-2. Reset Functions 27
- 8.5 Global Resources 28
- 8.6 Per-Port Resources 28
- 8.7 Device Interrupts 29
- 8.8 Serial Interface 31
- 8.9 Link Aggregation (IMUX) 31
- Sequence 01 32
- Sequence 02 32
- 8.9.2 IMUX Command Protocol 34
- 8.9.4 Data Transfer 36
- 8.10 Connections and Queues 37
- 8.11 Arbiter 38
- 8.12 Flow Control 39
- 8.13.1 DTE and DCE Mode 43
- 8.14 Ethernet MAC 46
- Figure 8-10. RMII Interface 47
- 8.15 BERT 48
- LoadVerify 49
- MatchVerify 50
- 802.3 MAC Frame 55
- Rate Adaption 55
- 9 DEVICE REGISTERS 60
- 9.1 Register Bit Maps 61
- 9.1.3 BERT Register Bit Map 62
- LI.TRX86SAPI 63
- LI.TRX86SAPIL 63
- TQOVFLS 64
- 9.1.6 MAC Register Bit Map 66
- 9.3 Arbiter Registers 81
- 9.4 BERT Registers 82
- 9.5.4 X.86 Registers 97
- 9.6.2 MAC Registers 124
- 10 FUNCTIONAL TIMING 140
- RXD[3:0] 141
- P R E A E M B L E 141
- 11 OPERATING PARAMETERS 142
- TXD[3:0] 144
- TXD[1:0] 146
- RXD[1:0] 147
- 11.7 SDRAM Timing 151
- LINK 4, CHANNEL 32 153
- LINK 1, CHANNEL 1 153
- LINK 2, CHANNEL 1 153
- Address Valid 156
- Data Valid 156
- 12 JTAG INFORMATION 159
- Capture-IR 161
- 12.2 Instruction Register 162
- 12.3 JTAG ID Codes 164
- 12.4 Test Registers 164
- 12.5 JTAG Functional Timing 165
- 13 PACKAGE INFORMATION 166
- 14 DOCUMENT REVISION HISTORY 167
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