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DS33Z41 Quad IMUX Ethernet Mapper
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Register Name:
SU.LPBK
Register Description:
Ethernet Interface Loopback Control Register
Register Address:
14Fh
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — — QLP
Default 0 0 0 0 0 0 0 0
Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is
looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is
removed.
Register Name:
SU.GCR
Register Description:
Ethernet Interface General Control Register
Register Address:
150h
Bit # 7 6 5 4 3 2 1 0
Name — — — — CRCS H10S ATFLOW JAME
Default 0 0 0 0 0 0 1 0
Bit 3: CRCS. If this bit is zero (default), the received MAC or Ethernet Frame CRC is stripped before the data is
encapsulated and transmitted on the serial interface. Data received from the serial interface is decapsulated, a
CRC is recalculated and appended to the packet for transmission to the Ethernet interface. If this bit is set to 1,
the CRC is not stripped from received packets prior to encapsulation and transmission to the serial interface, and
data received from the serial interface is decapsulated directly. No CRC recalculation is performed on data
received from the serial interface. Note that the maximum packet size supported by the Ethernet interface is still
2016 (this includes the 4 bytes of CRC).
Bit 2: H10S. This bit controls the 10/100 selection for RMII and DCE Mode. When in RMII mode, setting this bit
to 1 will cause the MAC will operate at 100Mbps and setting this bit to zero will cause the MAC to operate at
10Mbps. When in DCE mode, the bit function is inverted; setting this bit to 1 will cause the MAC to operate at
10Mbps. In DTE and MII mode, the MAC determines the data rate from the incoming TX_CLK and RX_CLK.
Bit 1: Automatic Flow Control Enable (ATFLOW). If this bit is set to 1, automatic flow control is enabled based
on the connection receive queue size and high watermarks. Pause frames are sent automatically in full duplex
mode. The pause time must be programmed through SU.MACFCR
. The jam sequence will not be sent
automatically in half duplex mode unless the JAME bit is set. This bit is applicable only in software mode.
Bit 0: Jam Enable (JAME). If this bit is set to 1, a Jam sequence is sent for a duration of 4 bytes. This function is
only valid in half duplex mode, and will only function if Automatic Flow Control is disabled. Note that if the receive
queue size is less than receive high threshold, setting a JAME will JAM one received frame. If JAME is set and
the receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties
below the threshold.
Note that SU.GCR
is only valid in the software mode. In hardware mode, pins are used to control Automatic flow
control and 100/10-speed selection.
- DS33Z41 1
- Quad IMUX Ethernet Mapper 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1 DESCRIPTION 7
- 2 FEATURE HIGHLIGHTS 8
- 2.6 SDRAM Interface 9
- 2.7 MAC Interface 9
- 2.9 Test and Diagnostics 9
- 3 APPLICATIONS 11
- 4 ACRONYMS AND GLOSSARY 12
- 5 MAJOR OPERATING MODES 13
- 6 BLOCK DIAGRAMS 13
- 7 PIN DESCRIPTIONS 14
- 8 FUNCTIONAL DESCRIPTION 22
- 8.1 Processor Interface 23
- 8.2 Clock Structure 24
- Table 8-2. Reset Functions 27
- 8.5 Global Resources 28
- 8.6 Per-Port Resources 28
- 8.7 Device Interrupts 29
- 8.8 Serial Interface 31
- 8.9 Link Aggregation (IMUX) 31
- Sequence 01 32
- Sequence 02 32
- 8.9.2 IMUX Command Protocol 34
- 8.9.4 Data Transfer 36
- 8.10 Connections and Queues 37
- 8.11 Arbiter 38
- 8.12 Flow Control 39
- 8.13.1 DTE and DCE Mode 43
- 8.14 Ethernet MAC 46
- Figure 8-10. RMII Interface 47
- 8.15 BERT 48
- LoadVerify 49
- MatchVerify 50
- 802.3 MAC Frame 55
- Rate Adaption 55
- 9 DEVICE REGISTERS 60
- 9.1 Register Bit Maps 61
- 9.1.3 BERT Register Bit Map 62
- LI.TRX86SAPI 63
- LI.TRX86SAPIL 63
- TQOVFLS 64
- 9.1.6 MAC Register Bit Map 66
- 9.3 Arbiter Registers 81
- 9.4 BERT Registers 82
- 9.5.4 X.86 Registers 97
- 9.6.2 MAC Registers 124
- 10 FUNCTIONAL TIMING 140
- RXD[3:0] 141
- P R E A E M B L E 141
- 11 OPERATING PARAMETERS 142
- TXD[3:0] 144
- TXD[1:0] 146
- RXD[1:0] 147
- 11.7 SDRAM Timing 151
- LINK 4, CHANNEL 32 153
- LINK 1, CHANNEL 1 153
- LINK 2, CHANNEL 1 153
- Address Valid 156
- Data Valid 156
- 12 JTAG INFORMATION 159
- Capture-IR 161
- 12.2 Instruction Register 162
- 12.3 JTAG ID Codes 164
- 12.4 Test Registers 164
- 12.5 JTAG Functional Timing 165
- 13 PACKAGE INFORMATION 166
- 14 DOCUMENT REVISION HISTORY 167
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