Maxim DS33R11 Manual de usuario descargar pdf (Pagina 12)

DS33R11DK/DS33ZH11DK

12 of 44

LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS

The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a

description of these signals, given in order of appearance on the PC board, from top to bottom then left to right

(with the board held so that the RS232 connector is on the left edge).

Table 2. Main Board PC Board Configuration

SILKSCREEN

REFERENCE

FUNCTION

BASIC

SETTING

SCHEMATIC

PAGE

DESCRIPTION

GROUND

(banana plug)

Power supply ground — 2

VDD 3.3V

(banana plug)

Power supply VDD — 2

System power. Always connected

to power supply. Connectors are

provided at the top left and bottom

right of board. Connect either set to

power supply.

J01 JTAG — 17

JTAG interface for Lattice EC3

FPGA.

J02

RS-232 DB9

connector

— 14

RS-232 DB9 connector, operates in

ASCII mode at 57.6K baud, 8, N, 1.

SW01 Reset 12 Drives reset controller U01.

DS01 LED — 15

Displays interrupt status of

DS33R11 (lit when interrupt is

asserted).

DS02 LED 7

Displays Queue overflow status of

DS33R11 (lit when Queue

overflows).

J04 OnCe BDM — 14 Debug connector for processor.

J03 Flash VPP 3.3V 14

Jumper for driving MMC2107 flash

VPP to 5V .

J05 JTAG — 10

JTAG interface for DS2155 portion

of DS33R11.

J06 JTAG — 11

JTAG interface for DS33Z11

portion of DS33R11.

Y01 Clock — 11

Oscillator for DS2155 portion of the

DS33R11.

J07, J08 Addr / Dat — 16

Address and Databus Test points

for DS33R11.

J09

Configuration pins

(See next two rows

for details.)

Schematic

Page16

Configuration switches for selecting device driver

behavior. Additional detail given below.

J09.2+J09.4 Removed Not installed

Pin J09.2 has been removed. Jumpering this pin to

J09.4 causes a conflict with J09.6 FPGA pin.

J09.4+J09.6 Driver Enable Installed

Enables device driver and interrupt handler when

jumper is installed.

J09.8+J09.10 RCLK select (FPGA) User selection

Causes device to select serial link TCLK = RCLK

when jumpered. When not jumpered TCLK =

MCLK.

Y02 Ethernet PHY Clock — 3

25.000MHz clock for DS33R11

Ethernet PHY.

JP03 Clock select

Pins 1+2

Jumpered

Must be set with pins 1+2

jumpered. SDRAM oscillator does

not meet jitter requirement of the

Ethernet PHY.

J10 Jumper Installed 10

Connects DS33R11 receive serial

lines.

J11 Jumper Installed 10

Connects DS33R11 transmit serial

lines.

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 43 44

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